From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 19 Mar 2019 12:55:02 +0000 (+0000)
Subject: Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc0-2' into... 
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=b98a66201dbc7cf3b962f4bb260f66100cc75578;p=qemu.git

Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc0-2' into staging

RISC-V Patches for 4.0-rc0, Part 2

This patch set contains three major sources of bug fixes:

* Jim has added support for GDB XML files, as well as fixing access to
  CSRs via the GDB stub.
* Alistair has rebased a large set of fixes from Michael that were still
  in his patch queue.  These fix bugs all over our tree, including:
    * Logging of PMP errors.
    * User ABI cleanups and fixes, most notably on RVE guests.
    * Fixes for interrupt emulation fidelity.
    * Improvements to the emulation fidelity of the sifive_u machine.
* Bin Meng has improved the emulation fidelity of the SiFive UART, which
  now supports both TX and RX interrupts (as well as setting the correct
  interrupt line).

# gpg: Signature made Tue 19 Mar 2019 12:42:11 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.0-rc0-2:
  riscv: sifive_u: Correct UART0's IRQ in the device tree
  riscv: sifive_uart: Generate TX interrupt
  target/riscv: Remove unused struct
  riscv: sifive_u: Allow up to 4 CPUs to be created
  RISC-V: Update load reservation comment in do_interrupt
  RISC-V: Convert trap debugging to trace events
  RISC-V: Add support for vectored interrupts
  RISC-V: Change local interrupts from edge to level
  RISC-V: linux-user support for RVE ABI
  elf: Add RISC-V PSABI ELF header defines
  RISC-V: Remove unnecessary disassembler constraints
  RISC-V: Allow interrupt controllers to claim interrupts
  RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
  riscv: pmp: Log pmp access errors as guest errors
  RISC-V: Add hooks to use the gdb xml files.
  RISC-V: Add debug support for accessing CSRs.
  RISC-V: Fixes to CSR_* register macros.
  RISC-V: Add 64-bit gdb xml files.
  RISC-V: Add 32-bit gdb xml files.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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b98a66201dbc7cf3b962f4bb260f66100cc75578