From: Marek Vasut <marex@denx.de>
Date: Mon, 16 Jan 2023 10:16:49 +0000 (+0100)
Subject: arm64: dts: imx8mp: Reorder clock to match fsl,imx6q-pcie.yaml
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=bae293e9e7a14cc5c6b6976865cec6ee41ed370d;p=linux.git

arm64: dts: imx8mp: Reorder clock to match fsl,imx6q-pcie.yaml

Reorder the PCIe clock in DT to match YAML DT schema. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index cd25913a385d9..ffa1331f831f2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1275,9 +1275,9 @@
 			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
 			reg-names = "dbi", "config";
 			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-				 <&clk IMX8MP_CLK_PCIE_ROOT>,
-				 <&clk IMX8MP_CLK_HSIO_AXI>;
-			clock-names = "pcie", "pcie_aux", "pcie_bus";
+				 <&clk IMX8MP_CLK_HSIO_AXI>,
+				 <&clk IMX8MP_CLK_PCIE_ROOT>;
+			clock-names = "pcie", "pcie_bus", "pcie_aux";
 			assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
 			assigned-clock-rates = <10000000>;
 			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;