From: Peter Maydell Date: Mon, 21 Jan 2019 12:49:48 +0000 (+0000) Subject: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190121' into... X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=bbca106776ab5decb01a0f101c67524546a1fcd2;p=qemu.git Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190121' into staging target-arm queue: * hw/char/stm32f2xx_usart: Do not update data register when device is disabled * hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node * target/arm: Allow Aarch32 exception return to switch from Mon->Hyp * ftgmac100: implement the new MDIO interface on Aspeed SoC * implement the ARMv8.3-PAuth extension * improve emulation of the ARM PMU # gpg: Signature made Mon 21 Jan 2019 10:42:11 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell " # gpg: aka "Peter Maydell " # gpg: aka "Peter Maydell " # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190121: (48 commits) target/arm: Implement PMSWINC target/arm: PMU: Set PMCR.N to 4 target/arm: PMU: Add instruction and cycle events target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] target/arm: Define FIELDs for ID_DFR0 target/arm: Implement PMOVSSET target/arm: Allow AArch32 access for PMCCFILTR target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Swap PMU values before/after migrations target/arm: Reorganize PMCCNTR accesses migration: Add post_save function to VMStateDescription target/arm: Tidy TBI handling in gen_a64_set_pc target/arm: Enable PAuth for user-only target/arm: Enable PAuth for -cpu max target/arm: Add PAuth system registers target/arm: Implement pauth_computepac target/arm: Implement pauth_addpac target/arm: Implement pauth_auth ... Signed-off-by: Peter Maydell --- bbca106776ab5decb01a0f101c67524546a1fcd2