From: Palmer Dabbelt Date: Wed, 30 Mar 2022 23:17:54 +0000 (-0700) Subject: RISC-V CPU Idle Support X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=bee7fbc38579ba86948689107518c855247d0b49;p=linux.git RISC-V CPU Idle Support This series adds RISC-V CPU Idle support using SBI HSM suspend function. The RISC-V SBI CPU idle driver added by this series is highly inspired from the ARM PSCI CPU idle driver. Special thanks Sandeep Tripathy for providing early feeback on SBI HSM support in all above projects (RISC-V SBI specification, OpenSBI, and Linux RISC-V). * palmer/riscv-idle: RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine dt-bindings: Add common bindings for ARM and RISC-V idle states cpuidle: Add RISC-V SBI CPU idle driver cpuidle: Factor-out power domain related code from PSCI domain driver RISC-V: Add SBI HSM suspend related defines RISC-V: Add arch functions for non-retentive suspend entry/exit RISC-V: Rename relocate() and make it global RISC-V: Enable CPU_IDLE drivers --- bee7fbc38579ba86948689107518c855247d0b49 diff --cc arch/riscv/include/asm/asm.h index 618d7c5af1a2d,48b4baa4d7069..8c2549b16ac06 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@@ -67,4 -67,31 +67,30 @@@ #error "Unexpected __SIZEOF_SHORT__" #endif + #ifdef __ASSEMBLY__ + + /* Common assembly source macros */ + + #ifdef CONFIG_XIP_KERNEL + .macro XIP_FIXUP_OFFSET reg + REG_L t0, _xip_fixup + add \reg, \reg, t0 + .endm + .macro XIP_FIXUP_FLASH_OFFSET reg + la t1, __data_loc - li t0, XIP_OFFSET_MASK - and t1, t1, t0 - li t1, XIP_OFFSET - sub t0, t0, t1 - sub \reg, \reg, t0 ++ REG_L t1, _xip_phys_offset ++ sub \reg, \reg, t1 ++ add \reg, \reg, t0 + .endm + _xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET ++_xip_phys_offset: .dword CONFIG_XIP_PHYS_ADDR + XIP_OFFSET + #else + .macro XIP_FIXUP_OFFSET reg + .endm + .macro XIP_FIXUP_FLASH_OFFSET reg + .endm + #endif /* CONFIG_XIP_KERNEL */ + + #endif /* __ASSEMBLY__ */ + #endif /* _ASM_RISCV_ASM_H */