From: Ovidiu Bunea <ovidiu.bunea@amd.com>
Date: Wed, 20 Sep 2023 19:25:46 +0000 (-0400)
Subject: drm/amd/display: Make driver backwards-compatible with non-IPS PMFW
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=c0af8c744e7e8f55ea2c26c80fe5c1cfee3a9359;p=linux.git

drm/amd/display: Make driver backwards-compatible with non-IPS PMFW

[why]
Driver needs to be compatible with PM FW that doesn't support IPS

[how]
Toggle internal control flag

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index c9c7baf45be36..b5acd7b01e40c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -744,16 +744,16 @@ static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
 	struct dc *dc = clk_mgr_base->ctx->dc;
 	uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
 
-	if (dc->debug.disable_ips == 0) {
+	if (dc->config.disable_ips == 0) {
 		val |= DMUB_IPS1_ALLOW_MASK;
 		val |= DMUB_IPS2_ALLOW_MASK;
-	} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS1) {
+	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
 		val = val & ~DMUB_IPS1_ALLOW_MASK;
 		val = val & ~DMUB_IPS2_ALLOW_MASK;
-	} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS2) {
+	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
 		val |= DMUB_IPS1_ALLOW_MASK;
 		val = val & ~DMUB_IPS2_ALLOW_MASK;
-	} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
+	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
 		val |= DMUB_IPS1_ALLOW_MASK;
 		val |= DMUB_IPS2_ALLOW_MASK;
 	}
@@ -1036,12 +1036,20 @@ void dcn35_clk_mgr_construct(
 		dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 				smu_dpm_clks.dpm_clks);
 
-	if (dcn35_smu_get_ips_supported(&clk_mgr->base)) {
-		ctx->dc->debug.ignore_pg = false;
-		ctx->dc->debug.dmcub_emulation = false;
-		ctx->dc->debug.disable_dpp_power_gate = false;
-		ctx->dc->debug.disable_hubp_power_gate = false;
-		ctx->dc->debug.disable_dsc_power_gate = false;
+	if (ctx->dc->config.disable_ips == 0) {
+		bool ips_support = false;
+
+		/*avoid call pmfw at init*/
+		ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
+		if (ips_support) {
+			ctx->dc->debug.ignore_pg = false;
+			ctx->dc->debug.disable_dpp_power_gate = false;
+			ctx->dc->debug.disable_hubp_power_gate = false;
+			ctx->dc->debug.disable_dsc_power_gate = false;
+		} else {
+			/*let's reset the config control flag*/
+			ctx->dc->config.disable_ips = 1; /*pmfw not support it, disable it all*/
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5e7f606a4cfcd..7e63bf0a63894 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -423,6 +423,7 @@ struct dc_config {
 	bool dc_mode_clk_limit_support;
 	bool EnableMinDispClkODM;
 	bool enable_auto_dpm_test_logs;
+	unsigned int disable_ips;
 };
 
 enum visual_confirm {
@@ -913,7 +914,6 @@ struct dc_debug_options {
 	enum det_size crb_alloc_policy;
 	int crb_alloc_policy_min_disp_count;
 	bool disable_z10;
-	unsigned int disable_ips;
 	bool enable_z9_disable_interface;
 	bool psr_skip_crtc_disable;
 	union dpia_debug_options dpia_debug;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index 6214866916c7e..693c7ba4b34d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -747,7 +747,6 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.disable_z10 = false,
 	.ignore_pg = true,
 	.psp_disabled_wa = true,
-	.disable_ips = true,
 	.ips2_eval_delay_us = 200,
 	.ips2_entry_delay_us = 400
 };