From: Eric Bernstein Date: Mon, 30 Jul 2018 21:43:23 +0000 (-0400) Subject: drm/amd/display: Fix null timing generator resource X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=c1127df9515ca781940927deffc5ae657ed73a5f;p=linux.git drm/amd/display: Fix null timing generator resource [Why] For some customer blending transition cases, the available pipe for second stream is a pipe index that is greater than the number of timing generators, which can cause a problem in acquire_first_free_pipe since it assumes same index for pipe and timing generator [How] Added logic to use last timing generator index if the pipe index is greater than number of timing generators. Acked-by: Alan Liu Signed-off-by: Eric Bernstein Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 3d45f6cae1f72..f7b47bf3ee590 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1885,6 +1885,12 @@ static int acquire_first_free_pipe( pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; pipe_ctx->pipe_idx = i; + if (i >= pool->timing_generator_count) { + int tg_inst = pool->timing_generator_count - 1; + + pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; + pipe_ctx->stream_res.opp = pool->opps[tg_inst]; + } pipe_ctx->stream = stream; return i;