From: Kishon Vijay Abraham I Date: Fri, 27 Apr 2018 12:09:04 +0000 (+0530) Subject: ARM: dts: dra7: Add high speed modes capability to MMC1/MMC2 dt node X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=c29fd489118a2abd2d17c49ae980e3c67fa6d004;p=linux.git ARM: dts: dra7: Add high speed modes capability to MMC1/MMC2 dt node While the supported UHS mode can be obtained from CAPA2 register, SD Host Controller Standard Specification doesn't define bits for MMC's HS200 and DDR mode capability. Add properties to indicate MMC HS200 and DDR speed mode capability in dt node. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ae2f8dd46328e..9dcd14edc2028 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1086,6 +1086,8 @@ status = "disabled"; pbias-supply = <&pbias_mmc_reg>; max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; }; hdqw1w: 1w@480b2000 { @@ -1104,6 +1106,9 @@ max-frequency = <192000000>; /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ sdhci-caps-mask = <0x7 0x0>; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + mmc-ddr-3_3v; }; mmc3: mmc@480ad000 {