From: AngeloGioacchino Del Regno Date: Wed, 29 Jun 2022 10:52:05 +0000 (+0200) Subject: clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1 X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=c39da7d0b40265eb4d0e9e5a1ea460ebc3f3185e;p=linux.git clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1 Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220629105205.173471-3-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 97657f255618c..ce7ac16a2f428 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -193,6 +193,8 @@ static u16 infra_ao_rst_ofs[] = { static u16 infra_ao_idx_map[] = { [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, + [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26, + [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27, [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10, };