From: Conor Dooley Date: Fri, 29 Jul 2022 11:11:17 +0000 (+0100) Subject: riscv: enable software resend of irqs X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=c45fc916c2b2cc2a0587659c18d6ceef9b7299be;p=linux.git riscv: enable software resend of irqs The PLIC specification does not describe the interrupt pendings bits as read-write, only that they "can be read". To allow for retriggering of interrupts (and the use of the irq debugfs interface) enable HARDIRQS_SW_RESEND for RISC-V. Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits Signed-off-by: Conor Dooley Acked-by: Marc Zyngier Acked-by: Palmer Dabbelt Tested-by: Palmer Dabbelt # on QEMU Reviewed-by: Björn Töpel Link: https://lore.kernel.org/r/20220729111116.259146-1-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt --- diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e84f2742b6bba..c56bc70158aca 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -70,6 +70,7 @@ config RISCV select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL if MMU && 64BIT select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO + select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL