From: Kishon Vijay Abraham I Date: Wed, 22 Jul 2020 11:03:08 +0000 (+0530) Subject: PCI: cadence: Allow pci_host_bridge to have custom pci_ops X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=c4c10c0125a705c606cb0cc85e18f13b490d026f;p=linux.git PCI: cadence: Allow pci_host_bridge to have custom pci_ops Certain platforms like TI's J721E allows only 32-bit configuration space access. In such cases pci_generic_config_read and pci_generic_config_write cannot be used. Add support in Cadence core to let pci_host_bridge have custom pci_ops. Link: https://lore.kernel.org/r/20200722110317.4744-7-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi --- diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 4e650c7a00323..f889914563fe8 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -506,7 +506,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) list_splice_init(&resources, &bridge->windows); bridge->dev.parent = dev; bridge->busnr = pcie->bus; - bridge->ops = &cdns_pcie_host_ops; + if (!bridge->ops) + bridge->ops = &cdns_pcie_host_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle;