From: Alex Deucher <alexander.deucher@amd.com>
Date: Wed, 12 Feb 2020 06:46:16 +0000 (-0500)
Subject: drm/amdgpu/soc15: fix xclk for raven
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=c657b936ea98630ef5ba4f130ab1ad5c534d0165;p=linux.git

drm/amdgpu/soc15: fix xclk for raven

It's 25 Mhz (refclk / 4).  This fixes the interpretation
of the rlc clock counter.

Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 15f3424a1ff79..2b488dfb2f21c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -272,7 +272,12 @@ static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
-	return adev->clock.spll.reference_freq;
+	u32 reference_clock = adev->clock.spll.reference_freq;
+
+	if (adev->asic_type == CHIP_RAVEN)
+		return reference_clock / 4;
+
+	return reference_clock;
 }