From: Martin Blumenstingl Date: Sat, 2 Jul 2022 23:12:20 +0000 (+0200) Subject: dt-bindings: mtd: intel: lgm-nand: Fix compatible string X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=c6d7ce0a7e0562846431dc3c7c390dde7d0c0c42;p=linux.git dt-bindings: mtd: intel: lgm-nand: Fix compatible string The driver which was added at the same time as the dt-bindings uses the compatible string "intel,lgm-ebunand". Use the same compatible string also in the dt-bindings and rename the bindings file accordingly. Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC") Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-2-martin.blumenstingl@googlemail.com --- diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml new file mode 100644 index 0000000000000..763ee3e1faf32 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/intel,lgm-ebunand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel LGM SoC NAND Controller Device Tree Bindings + +allOf: + - $ref: "nand-controller.yaml" + +maintainers: + - Ramuthevar Vadivel Murugan + +properties: + compatible: + const: intel,lgm-ebunand + + reg: + maxItems: 6 + + reg-names: + items: + - const: ebunand + - const: hsnand + - const: nand_cs0 + - const: nand_cs1 + - const: addr_sel0 + - const: addr_sel1 + + clocks: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^nand@[a-f0-9]+$": + type: object + properties: + reg: + minimum: 0 + maximum: 7 + + nand-ecc-mode: true + + nand-ecc-algo: + const: hw + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - clocks + - dmas + - dma-names + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + nand-controller@e0f00000 { + compatible = "intel,lgm-ebunand"; + reg = <0xe0f00000 0x100>, + <0xe1000000 0x300>, + <0xe1400000 0x8000>, + <0xe1c00000 0x1000>, + <0x17400000 0x4>, + <0x17c00000 0x4>; + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", + "addr_sel0", "addr_sel1"; + clocks = <&cgu0 125>; + dmas = <&dma0 8>, <&dma0 9>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml deleted file mode 100644 index 30e0c66ab0eb7..0000000000000 --- a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml +++ /dev/null @@ -1,99 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel LGM SoC NAND Controller Device Tree Bindings - -allOf: - - $ref: "nand-controller.yaml" - -maintainers: - - Ramuthevar Vadivel Murugan - -properties: - compatible: - const: intel,lgm-nand - - reg: - maxItems: 6 - - reg-names: - items: - - const: ebunand - - const: hsnand - - const: nand_cs0 - - const: nand_cs1 - - const: addr_sel0 - - const: addr_sel1 - - clocks: - maxItems: 1 - - dmas: - maxItems: 2 - - dma-names: - items: - - const: tx - - const: rx - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - -patternProperties: - "^nand@[a-f0-9]+$": - type: object - properties: - reg: - minimum: 0 - maximum: 7 - - nand-ecc-mode: true - - nand-ecc-algo: - const: hw - - additionalProperties: false - -required: - - compatible - - reg - - reg-names - - clocks - - dmas - - dma-names - - "#address-cells" - - "#size-cells" - -additionalProperties: false - -examples: - - | - nand-controller@e0f00000 { - compatible = "intel,lgm-nand"; - reg = <0xe0f00000 0x100>, - <0xe1000000 0x300>, - <0xe1400000 0x8000>, - <0xe1c00000 0x1000>, - <0x17400000 0x4>, - <0x17c00000 0x4>; - reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", - "addr_sel0", "addr_sel1"; - clocks = <&cgu0 125>; - dmas = <&dma0 8>, <&dma0 9>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - nand-ecc-mode = "hw"; - }; - }; - -...