From: Daniel Schultz <d.schultz@phytec.de>
Date: Mon, 5 Mar 2018 12:45:11 +0000 (+0100)
Subject: ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=c887f5b0210c5c7d30e2da47c37798eb6f37f563;p=linux.git

ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som

The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---

diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index f13bcb1cd3d98..aaab2d171ffe1 100644
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -151,6 +151,7 @@
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			enet-phy-lane-no-swap;
+			ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
 		};
 	};
 };