From: Anshuman Khandual Date: Wed, 14 Jun 2023 06:59:45 +0000 (+0530) Subject: arm64/sysreg: Convert TRBBASER_EL1 register to automatic generation X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=cbaf0cf005f0de92532b713fd8f7497a129f588b;p=linux.git arm64/sysreg: Convert TRBBASER_EL1 register to automatic generation This converts TRBBASER_EL1 register to automatic generation without causing any functional change. Cc: Will Deacon Cc: Marc Zyngier Cc: Mark Brown Cc: Rob Herring Cc: Suzuki K Poulose Cc: James Morse Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20230614065949.146187-11-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas --- diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6b3204fbad22b..98aa015f6db82 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -227,14 +227,11 @@ /*** End of Statistical Profiling Extension ***/ -#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2) #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) -#define TRBBASER_EL1_BASE_MASK GENMASK_ULL(63, 12) -#define TRBBASER_EL1_BASE_SHIFT 12 #define TRBSR_EL1_EC_MASK GENMASK(31, 26) #define TRBSR_EL1_EC_SHIFT 26 #define TRBSR_EL1_IRQ BIT(22) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ec493e43988c2..e51eec07e7c3e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2277,3 +2277,8 @@ EndSysreg Sysreg TRBPTR_EL1 3 0 9 11 1 Field 63:0 PTR EndSysreg + +Sysreg TRBBASER_EL1 3 0 9 11 2 +Field 63:12 BASE +Res0 11:0 +EndSysreg