From: Randy Dunlap Date: Wed, 25 Jan 2023 03:22:21 +0000 (-0800) Subject: cxl: fix spelling mistakes X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=cbbd05d036e91b9dd976af4382f6c8d91b69b38a;p=linux.git cxl: fix spelling mistakes Correct spelling mistakes (reported by codespell). Signed-off-by: Randy Dunlap Cc: Alison Schofield Cc: Vishal Verma Cc: Ira Weiny Cc: Ben Widawsky Cc: Dan Williams Cc: linux-cxl@vger.kernel.org Reviewed-by: Vishal Verma Reviewed-by: Alison Schofield Link: https://lore.kernel.org/r/20230125032221.21277-1-rdunlap@infradead.org Signed-off-by: Dan Williams --- diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 0ac53c422c318..9e709ecba50fc 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -116,7 +116,7 @@ config CXL_REGION_INVALIDATION_TEST depends on CXL_REGION help CXL Region management and security operations potentially invalidate - the content of CPU caches without notifiying those caches to + the content of CPU caches without notifying those caches to invalidate the affected cachelines. The CXL Region driver attempts to invalidate caches when those events occur. If that invalidation fails the region will fail to enable. Reasons for cache diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index ad0849af42d79..6927149f2a161 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -19,7 +19,7 @@ struct cxl_cxims_data { /* * Find a targets entry (n) in the host bridge interleave list. - * CXL Specfication 3.0 Table 9-22 + * CXL Specification 3.0 Table 9-22 */ static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw, int ig) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 410c036c09fa5..609aa6801b149 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1164,7 +1164,7 @@ static struct cxl_port *find_cxl_port_at(struct cxl_port *parent_port, } /* - * All users of grandparent() are using it to walk PCIe-like swich port + * All users of grandparent() are using it to walk PCIe-like switch port * hierarchy. A PCIe switch is comprised of a bridge device representing the * upstream switch port and N bridges representing downstream switch ports. When * bridges stack the grand-parent of a downstream switch port is another diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 60828d01972ac..3482a9e6d2f22 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -414,7 +414,7 @@ static ssize_t interleave_granularity_store(struct device *dev, * When the host-bridge is interleaved, disallow region granularity != * root granularity. Regions with a granularity less than the root * interleave result in needing multiple endpoints to support a single - * slot in the interleave (possible to suport in the future). Regions + * slot in the interleave (possible to support in the future). Regions * with a granularity greater than the root interleave result in invalid * DPA translations (invalid to support). */