From: Rajendra Nayak Date: Tue, 30 Jun 2020 08:45:12 +0000 (+0530) Subject: arm64: dts: sc7180: Add sdhc opps and power-domains X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=ccc6e8a1d6e936643e4b7e5b35f9456a7e36365c;p=linux.git arm64: dts: sc7180: Add sdhc opps and power-domains Add the power domain supporting performance state and the corresponding OPP tables for the sdhc device on sc7180. Reviewed-by: Matthias Kaehlcke Signed-off-by: Rajendra Nayak Link: https://lore.kernel.org/r/1593506712-24557-5-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 725a47a977cbd..126e2fce26c1a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -684,6 +684,8 @@ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&sdhc1_opp_table>; bus-width = <8>; non-removable; @@ -695,6 +697,20 @@ mmc-hs400-enhanced-strobe; status = "disabled"; + + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; }; qup_opp_table: qup-opp-table { @@ -2460,10 +2476,26 @@ clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; clock-names = "core", "iface"; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; status = "disabled"; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; }; qspi_opp_table: qspi-opp-table {