From: Varadarajan Narayanan Date: Thu, 31 Aug 2023 09:28:53 +0000 (+0530) Subject: clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=ccd8ab030643040600a663edde56b434b6f4fb6c;p=linux.git clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks IPQ5332's GPLL0's nominal/turbo frequency is 800MHz. This must not be scaled based on the requirement of dependent clocks. Hence remove the CLK_SET_RATE_PARENT flag. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Varadarajan Narayanan Reviewed-by: Kathiravan T Link: https://lore.kernel.org/r/1693474133-10467-1-git-send-email-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index b02026f8549b2..b836159fbdefa 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -71,7 +71,6 @@ static struct clk_fixed_factor gpll0_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -85,7 +84,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, };