From: Lijo Lazar <lijo.lazar@amd.com>
Date: Mon, 8 Aug 2022 05:50:36 +0000 (+0530)
Subject: drm/amdgpu: Use status register for partition mode
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=cd321e6fd611db983fb7cdb52daf089fabe4f9c7;p=linux.git

drm/amdgpu: Use status register for partition mode

Program partition status register to reflect the current partition mode.
Partition capability register is for capability and is a one-time setting.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
index bcd3e08d01cd2..ef0b557e9b3eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
@@ -418,20 +418,13 @@ static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev,
 
 static enum amdgpu_gfx_partition nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev)
 {
-	u32 tmp;
+	u32 tmp, px;
 
-	tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_CAP);
+	tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
+	px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
+			   PARTITION_MODE);
 
-	if (REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_CAP, SPX_SUPPORT))
-		return AMDGPU_SPX_PARTITION_MODE;
-	else if (REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_CAP, DPX_SUPPORT))
-		return AMDGPU_DPX_PARTITION_MODE;
-	else if (REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_CAP, TPX_SUPPORT))
-		return AMDGPU_TPX_PARTITION_MODE;
-	else if (REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_CAP, CPX_SUPPORT))
-		return AMDGPU_CPX_PARTITION_MODE;
-	else
-		return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;
+	return ffs(px);
 }
 
 static void nbio_v7_9_set_compute_partition_mode(struct amdgpu_device *adev,
@@ -439,11 +432,14 @@ static void nbio_v7_9_set_compute_partition_mode(struct amdgpu_device *adev,
 {
 	u32 tmp;
 
-	tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_CAP);
-	tmp &= ~0x1f;
-	tmp |= 1 << mode;
+	/* Each bit represents DPX,TPX,QPX,CPX mode. No bit set means default
+	 * SPX mode.
+	 */
+	tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
+	tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
+			    PARTITION_MODE, mode ? BIT(mode - 1) : mode);
 
-	WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_CAP, tmp);
+	WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS, tmp);
 }
 
 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {