From: Elaine Zhang Date: Tue, 18 Oct 2022 15:14:02 +0000 (+0200) Subject: clk: rockchip: add register offset of the cores select parent X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=cf87691f143e6cc5727767b02ec2be3725534a5d;p=linux.git clk: rockchip: add register offset of the cores select parent The cores select parent register is special on RK3588. Signed-off-by: Elaine Zhang Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 47288197c9d7e..11aa2259b5324 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -166,10 +166,16 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, } } /* select alternate parent */ - writel(HIWORD_UPDATE(reg_data->mux_core_alt, - reg_data->mux_core_mask, - reg_data->mux_core_shift), - cpuclk->reg_base + reg_data->core_reg[0]); + if (reg_data->mux_core_reg) + writel(HIWORD_UPDATE(reg_data->mux_core_alt, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->mux_core_reg); + else + writel(HIWORD_UPDATE(reg_data->mux_core_alt, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->core_reg[0]); spin_unlock_irqrestore(cpuclk->lock, flags); return 0; @@ -202,10 +208,16 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, * primary parent by the extra dividers that were needed for the alt. */ - writel(HIWORD_UPDATE(reg_data->mux_core_main, - reg_data->mux_core_mask, - reg_data->mux_core_shift), - cpuclk->reg_base + reg_data->core_reg[0]); + if (reg_data->mux_core_reg) + writel(HIWORD_UPDATE(reg_data->mux_core_main, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->mux_core_reg); + else + writel(HIWORD_UPDATE(reg_data->mux_core_main, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->core_reg[0]); /* remove dividers */ for (i = 0; i < reg_data->num_cores; i++) { diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index ee01739e4a7cb..43a37a43b6f35 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -389,6 +389,8 @@ struct rockchip_cpuclk_rate_table { * @div_core_shift[]: cores divider offset used to divide the pll value * @div_core_mask[]: cores divider mask * @num_cores: number of cpu cores + * @mux_core_reg: register offset of the cores select parent + * @mux_core_alt: mux value to select alternate parent * @mux_core_main: mux value to select main parent of core * @mux_core_shift: offset of the core multiplexer * @mux_core_mask: core multiplexer mask @@ -398,6 +400,7 @@ struct rockchip_cpuclk_reg_data { u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; int num_cores; + int mux_core_reg; u8 mux_core_alt; u8 mux_core_main; u8 mux_core_shift;