From: Rob Herring Date: Fri, 21 Aug 2020 03:54:04 +0000 (-0600) Subject: PCI: dwc: Ensure FAST_LINK_MODE is cleared X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=cff9244432e833710a14ed597d33615d77934a9d;p=linux.git PCI: dwc: Ensure FAST_LINK_MODE is cleared "Fast Link Mode" is a simulation environment speed up setting which should never be set and the default is not set. However some Amlogic platforms have it set (by firmware presumably). See commit 87dccf09323f ("PCI: amlogic: meson: Don't use FAST_LINK_MODE to set up link") for more information. Let's clear it in core DWC code so we can drop some vendor specific code. Link: https://lore.kernel.org/r/20200821035420.380495-25-robh@kernel.org Signed-off-by: Rob Herring Signed-off-by: Lorenzo Pieralisi Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas --- diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index e957a726be85c..90dc1674aae55 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -559,6 +559,9 @@ void dw_pcie_setup(struct dw_pcie *pci) dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? "enabled" : "disabled"); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + val &= ~PORT_LINK_FAST_LINK_MODE; + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); of_property_read_u32(np, "num-lanes", &pci->num_lanes); if (!pci->num_lanes) { @@ -567,7 +570,7 @@ void dw_pcie_setup(struct dw_pcie *pci) } /* Set the number of lanes */ - val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + val &= ~PORT_LINK_FAST_LINK_MODE; val &= ~PORT_LINK_MODE_MASK; switch (pci->num_lanes) { case 1: diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 6d3bec33de98e..66815581b4984 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -36,6 +36,7 @@ #define PCIE_PORT_LINK_CONTROL 0x710 #define PORT_LINK_DLL_LINK_EN BIT(5) +#define PORT_LINK_FAST_LINK_MODE BIT(7) #define PORT_LINK_MODE_MASK GENMASK(21, 16) #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)