From: James Clark Date: Thu, 3 Feb 2022 11:53:35 +0000 (+0000) Subject: coresight: no-op refactor to make INSTP0 check more idiomatic X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d05bbad0130ff86b802e5cd6acbb6cac23b841b8;p=linux.git coresight: no-op refactor to make INSTP0 check more idiomatic The spec says this: P0 tracing support field. The permitted values are: 0b00 Tracing of load and store instructions as P0 elements is not supported. 0b11 Tracing of load and store instructions as P0 elements is supported, so TRCCONFIGR.INSTP0 is supported. All other values are reserved. The value we are looking for is 0b11 so simplify this. The double read and && was a bit obfuscated. Suggested-by: Suzuki Poulose Signed-off-by: James Clark Link: https://lore.kernel.org/r/20220203115336.119735-2-james.clark@arm.com Signed-off-by: Suzuki K Poulose --- diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index bf18128cf5ded..e2eebd8652416 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1091,7 +1091,7 @@ static void etm4_init_arch_data(void *info) etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); /* INSTP0, bits[2:1] P0 tracing support field */ - if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) + if (BMVAL(etmidr0, 1, 2) == 0b11) drvdata->instrp0 = true; else drvdata->instrp0 = false;