From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Fri, 12 Apr 2024 17:58:18 +0000 (+0300)
Subject: drm/i915: Enable per-lane DP drive settings for bxt/glk
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d08184aa906508fc1f772b1d0b4f44a33c086f33;p=linux.git

drm/i915: Enable per-lane DP drive settings for bxt/glk

Now the bxt/glk PHY code is ready for per-lane drive settings
so enable it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240412175818.29217-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index fb84ca98bb7ab..947575140059d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -334,7 +334,7 @@ static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
 	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
-		DISPLAY_VER(i915) >= 11;
+		DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915);
 }
 
 /* 128b/132b */