From: Alexander Wagner Date: Tue, 20 Apr 2021 08:00:08 +0000 (+0200) Subject: hw/riscv: Fix OT IBEX reset vector X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d11e316d843b2d370a547700407947356e4117cb;p=qemu.git hw/riscv: Fix OT IBEX reset vector The IBEX documentation [1] specifies the reset vector to be "the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte". [1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst Signed-off-by: Alexander Wagner Reviewed-by: Alistair Francis Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de Signed-off-by: Alistair Francis --- diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 557d73726b..7545dcda9c 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -119,7 +119,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); - object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); /* Boot ROM */