From: chunhui dai Date: Mon, 25 Feb 2019 02:09:10 +0000 (+0800) Subject: clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d3174bc836d5aadc871f74ed496694c5ea27b104;p=linux.git clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel The MUX clock of dpi1_sel should select the closet clock for itself. We could add this flag to enable this function of MUX in CCF. Signed-off-by: chunhui dai Signed-off-by: wangyan wang Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index ab6ab07f53e64..905a2316f6a7f 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -535,8 +535,8 @@ static const struct mtk_composite top_muxes[] = { 0x0080, 8, 2, 15), MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23), - MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, - 0x0080, 24, 2, 31), + MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, + 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST), MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7),