From: Matt Roper Date: Fri, 21 Apr 2023 14:50:05 +0000 (-0700) Subject: drm/xe: Fix xe_mmio_rmw32 operation X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d33dc1dc29cab7871f9b0adee7b94b4dc5de5cb1;p=linux.git drm/xe: Fix xe_mmio_rmw32 operation xe_mmio_rmw32 was failing to invert the passed in mask, resulting in a register update that wasn't the expected RMW operation. Fortunately the impact of this mistake was limited, since this function isn't heavily used in Xe right now; this will mostly fix some GuC PM interrupt unmasking. v2: - Rename parameters as 'clr' and 'set' to clarify semantics. (Lucas) Cc: Lucas De Marchi Cc: Maarten Lankhorst Reviewed-by: Lucas De Marchi Link: https://lore.kernel.org/r/20230421145006.10940-1-matthew.d.roper@intel.com Signed-off-by: Matt Roper Signed-off-by: Rodrigo Vivi --- diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h index 354be6fae0d47..be7ba2813d58d 100644 --- a/drivers/gpu/drm/xe/xe_mmio.h +++ b/drivers/gpu/drm/xe/xe_mmio.h @@ -42,13 +42,13 @@ static inline u32 xe_mmio_read32(struct xe_gt *gt, u32 reg) return readl(gt->mmio.regs + reg); } -static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 mask, - u32 val) +static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 clr, + u32 set) { u32 old, reg_val; old = xe_mmio_read32(gt, reg); - reg_val = (old & mask) | val; + reg_val = (old & ~clr) | set; xe_mmio_write32(gt, reg, reg_val); return old;