From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Sun, 10 Apr 2005 14:40:58 +0000 (+0000)
Subject: fixed MMU bug on code page boundary
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d39c0b990a243fba280eb4222daf685491431a5b;p=qemu.git

fixed MMU bug on code page boundary


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1362 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 543ed927b6..f93c3b1ca4 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1395,24 +1395,24 @@ static void disas_sparc_insn(DisasContext * dc)
 		    if (!supervisor(dc))
 			goto priv_insn;
 		    gen_op_sta(insn, 0, 4, 0);
-		    break;
+                    break;
 		case 0x15:
 		    if (!supervisor(dc))
 			goto priv_insn;
 		    gen_op_stba(insn, 0, 1, 0);
-		    break;
+                    break;
 		case 0x16:
 		    if (!supervisor(dc))
 			goto priv_insn;
 		    gen_op_stha(insn, 0, 2, 0);
-		    break;
+                    break;
 		case 0x17:
 		    if (!supervisor(dc))
 			goto priv_insn;
                     flush_T2(dc);
 		    gen_movl_reg_T2(rd + 1);
 		    gen_op_stda(insn, 0, 8, 0);
-		    break;
+                    break;
 #endif
 		default:
 		case 0x0e: /* V9 stx */
@@ -1545,6 +1545,10 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
 	/* if the next PC is different, we abort now */
 	if (dc->pc != (last_pc + 4))
 	    break;
+        /* if we reach a page boundary, we stop generation so that the
+           PC of a TT_TFAULT exception is always in the right page */
+        if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
+            break;
         /* if single step mode, we generate only one instruction and
            generate an exception */
         if (env->singlestep_enabled) {