From: Marc Zyngier Date: Sun, 10 Jul 2022 08:51:20 +0000 (+0100) Subject: Merge branch irq/plic-masking into irq/irqchip-next X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d4a930a08c2664662e08e9a895c4d10fd30c04d9;p=linux.git Merge branch irq/plic-masking into irq/irqchip-next * irq/plic-masking: : . : SiFive PLIC optimisations from Samuel Holland: : : "This series removes the spinlocks and cpumask operations from the PLIC : driver's hot path. As far as I know, using the priority to mask : interrupts is an intended usage and will work on all existing : implementations. [...]" : . irqchip/sifive-plic: Separate the enable and mask operations irqchip/sifive-plic: Make better use of the effective affinity mask PCI: hv: Take a const cpumask in hv_compose_msi_req_get_cpu() genirq: Provide an IRQ affinity mask in non-SMP configs genirq: Return a const cpumask from irq_data_get_affinity_mask genirq: Add and use an irq_data_update_affinity helper genirq: Refactor accessors to use irq_data_get_affinity_mask genirq: Drop redundant irq_init_effective_affinity genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMP genirq: GENERIC_IRQ_IPI depends on SMP irqchip/mips-gic: Only register IPI domain when SMP is enabled Signed-off-by: Marc Zyngier --- d4a930a08c2664662e08e9a895c4d10fd30c04d9