From: Maxim Kiselev Date: Wed, 15 Jan 2020 07:38:11 +0000 (+0300) Subject: gpio: mvebu: clear irq in edge cause register before unmask edge irq X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d5331ec2cc6e8b79b8b0027091d1ebb395e833b5;p=linux.git gpio: mvebu: clear irq in edge cause register before unmask edge irq When input GPIO set from 0 to 1, the interrupt bit asserted in the GPIO Interrupt Cause Register (ICR) even if the corresponding interrupt masked in the GPIO Interrupt Mask Register. Because interrupt mask register only affects assertion of the interrupt bits in Main Interrupt Cause Register and it does not affect the setting of bits in the GPIO ICR. So, there is problem, when we unmask interrupt with already asserted bit in the GPIO ICR, then false interrupt immediately occurs even if GPIO don't change their value since last unmask. Signed-off-by: Maxim Kiselev Link: https://lore.kernel.org/r/20200115073811.24438-1-bigunclemax@gmail.com Signed-off-by: Linus Walleij --- diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c index f0fd82b3417cf..d2b999c7987f1 100644 --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c @@ -431,6 +431,7 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) u32 mask = d->mask; irq_gc_lock(gc); + mvebu_gpio_write_edge_cause(mvchip, ~mask); ct->mask_cache_priv |= mask; mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); irq_gc_unlock(gc);