From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 8 Sep 2015 16:38:43 +0000 (+0100)
Subject: hw/intc/arm_gic: Actually set the active bits for active interrupts
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d5523a13656fb8df902a15a9fd8bd652b85e97e0;p=qemu.git

hw/intc/arm_gic: Actually set the active bits for active interrupts

Although we were correctly handling interrupts becoming active
and then inactive, we weren't actually exposing this to the guest
by setting the 'active' flag for the interrupt, so reads
of GICD_ICACTIVERn and GICD_ISACTIVERn would generally incorrectly
return zeroes. Correct this oversight.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1438089748-5528-6-git-send-email-peter.maydell@linaro.org
---

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 9daa8cd44f..2df550c01b 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -262,6 +262,7 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
     }
 
     s->running_priority[cpu] = prio;
+    GIC_SET_ACTIVE(irq, 1 << cpu);
 }
 
 static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
@@ -536,6 +537,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
      */
 
     gic_drop_prio(s, cpu, group);
+    GIC_CLEAR_ACTIVE(irq, cm);
     gic_update(s);
 }