From: Amelie Delaunay Date: Wed, 6 Oct 2021 09:53:55 +0000 (+0200) Subject: ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151 X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d5670adf5cffe9075b906e122b7250d02cf9fd91;p=linux.git ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151 [ Upstream commit db7be2cb87ae65e2d033a9f61f7fb94bce505177 ] Referring to the note under USBH reset and clocks chapter of RM0436, "In order to access USBH_OHCI registers it is necessary to activate the USB clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m). The point is, when USBPHYC PLL is not enabled, OHCI register access freezes the resume from STANDBY. It is the case when dual USBH is enabled, instead of OTG + single USBH. When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL is enabled and OHCI register access is OK. This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue Signed-off-by: Sasha Levin --- diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 6992a4b0ba79b..f693a7d242471 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1452,7 +1452,7 @@ usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; - clocks = <&rcc USBH>; + clocks = <&rcc USBH>, <&usbphyc>; resets = <&rcc USBH_R>; interrupts = ; status = "disabled";