From: Fabrizio Castro Date: Tue, 18 Jul 2023 19:24:50 +0000 (+0100) Subject: spi: rzv2m-csi: Squash timing settings into one statement X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d5737d12779a171e76ad07635d1ed06a22009da7;p=linux.git spi: rzv2m-csi: Squash timing settings into one statement Register CLKSEL hosts the configuration for both clock polarity and data phase, and both values can be set in one write operation. Squash the clock polarity and data phase register writes into one statement, for efficiency. Signed-off-by: Fabrizio Castro Suggested-by: Andy Shevchenko Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230718192453.543549-2-fabrizio.castro.jz@renesas.com Signed-off-by: Mark Brown --- diff --git a/drivers/spi/spi-rzv2m-csi.c b/drivers/spi/spi-rzv2m-csi.c index 038f1486b7d7b..faf5898bc3e01 100644 --- a/drivers/spi/spi-rzv2m-csi.c +++ b/drivers/spi/spi-rzv2m-csi.c @@ -38,6 +38,7 @@ /* CSI_CLKSEL */ #define CSI_CLKSEL_CKP BIT(17) #define CSI_CLKSEL_DAP BIT(16) +#define CSI_CLKSEL_MODE (CSI_CLKSEL_CKP|CSI_CLKSEL_DAP) #define CSI_CLKSEL_SLAVE BIT(15) #define CSI_CLKSEL_CKS GENMASK(14, 1) @@ -408,10 +409,8 @@ static int rzv2m_csi_setup(struct spi_device *spi) writel(CSI_MODE_SETUP, csi->base + CSI_MODE); /* Setup clock polarity and phase timing */ - rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_CKP, - !(spi->mode & SPI_CPOL)); - rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_DAP, - !(spi->mode & SPI_CPHA)); + rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_MODE, + ~spi->mode & SPI_MODE_X_MASK); /* Setup serial data order */ rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_DIR,