From: Alistair Francis <alistair.francis@wdc.com>
Date: Thu, 1 Apr 2021 15:17:48 +0000 (-0400)
Subject: target/riscv: Fix 32-bit HS mode access permissions
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d6f20dacea5147a9136ec3ecc7124440c16ba862;p=qemu.git

target/riscv: Fix 32-bit HS mode access permissions

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
---

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1938bdca7d..6a39c4aa96 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -181,7 +181,11 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
 static RISCVException hmode32(CPURISCVState *env, int csrno)
 {
     if (!riscv_cpu_is_32bit(env)) {
-        return RISCV_EXCP_NONE;
+        if (riscv_cpu_virt_enabled(env)) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        } else {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
     }
 
     return hmode(env, csrno);