From: Sebastian Huber Date: Fri, 24 May 2024 11:32:56 +0000 (+0200) Subject: hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=d9aff83ad569714ec1b05176942a80fd80e062b7;p=qemu.git hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn According to the GICv2 specification section 4.3.12, "Interrupt Processor Targets Registers, GICD_ITARGETSRn": "Any change to a CPU targets field value: [...] * Has an effect on any pending interrupts. This means: - adding a CPU interface to the target list of a pending interrupt makes that interrupt pending on that CPU interface - removing a CPU interface from the target list of a pending interrupt removes the pending state of that interrupt on that CPU interface." Signed-off-by: Sebastian Huber Message-id: 20240524113256.8102-3-sebastian.huber@embedded-brains.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 04e5a11660..806832439b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1410,6 +1410,13 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, value = ALL_CPU_MASK; } s->irq_target[irq] = value & ALL_CPU_MASK; + if (irq >= GIC_INTERNAL && s->irq_state[irq].pending) { + /* + * Changing the target of an interrupt that is currently + * pending updates the set of CPUs it is pending on. + */ + s->irq_state[irq].pending = value & ALL_CPU_MASK; + } } } else if (offset < 0xf00) { /* Interrupt Configuration. */