From: Stephen Boyd Date: Fri, 31 Jan 2020 21:14:26 +0000 (-0800) Subject: Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', 'clk... X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=db865ee447d46eccd641dc70c7f9acc231a3141e;p=linux.git Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', 'clk-freescale' and 'clk-qoriq' into clk-next - Support for Xilinx Versal platform clks - Display clk controller on qcom sc7180 - Video clk controller on qcom sc7180 - Graphics clk controller on qcom sc7180 - CPU PLLs for qcom msm8916 - Fixes for clk controllers on qcom msm8998 SoCs - Move qcom msm8974 gfx3d clk to RPM control - Display port clk support on qcom sdm845 SoCs - Global clk controller on qcom ipq6018 - Adjust composite clk to new way of describing clk parents - Add a driver for BCLK of Freescale SAI cores * clk-imx: (32 commits) clk: imx: Add support for i.MX8MP clock driver dt-bindings: imx: Add clock binding doc for i.MX8MP clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API clk: imx: imx8mq: Switch to clk_hw based API clk: imx: imx8mm: Switch to clk_hw based API clk: imx: imx8mn: Switch to clk_hw based API clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API clk: imx: gate3: Switch to clk_hw based API clk: imx: add hw API imx_clk_hw_mux2_flags clk: imx: add imx_unregister_hw_clocks clk: imx: clk-composite-8m: Switch to clk_hw based API clk: imx: clk-pll14xx: Switch to clk_hw based API clk: imx7up: Rename the clks to hws clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based clk: imx: Rename sccg and frac pll register to suggest clk_hw clk: imx: imx7ulp composite: Rename to show is clk_hw based clk: imx: pllv2: Switch to clk_hw based API clk: imx: pllv1: Switch to clk_hw based API ... * clk-ti: clk: ti: clkctrl: Fix hidden dependency to node name clk: ti: add clkctrl data dra7 sgx clk: ti: omap5: Add missing AESS clock clk: ti: dra7: fix parent for gmac_clkctrl clk: ti: dra7: add vpe clkctrl data clk: ti: dra7: add cam clkctrl data dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock * clk-xilinx: clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag clk: zynqmp: Fix divider calculation clk: zynqmp: Add support for get max divider clk: zynqmp: Warn user if clock user are more than allowed clk: zynqmp: Extend driver for versal dt-bindings: clock: Add bindings for versal clock driver * clk-nvidia: clk: tegra20/30: Explicitly set parent clock for Video Decoder clk: tegra20/30: Don't pre-initialize displays parent clock clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe() clk: tegra: Mark fuse clock as critical * clk-qcom: (35 commits) clk: qcom: rpmh: Sort OF match table dt-bindings: fix warnings in validation of qcom,gcc.yaml dt-binding: fix compilation error of the example in qcom,gcc.yaml clk: qcom: Add ipq6018 Global Clock Controller support clk: qcom: Add DT bindings for ipq6018 gcc clock controller clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks clk: qcom: rpmh: Add IPA clock for SC7180 clk: qcom: rpmh: skip undefined clocks when registering clk: qcom: Add video clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings clk: qcom: Add graphics clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent clk: qcom: Add display clock controller driver for SC7180 dt-bindings: clock: Introduce QCOM sc7180 display clock bindings dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration clk: qcom: alpha-pll: Remove useless read from set rate ... * clk-freescale: clk: fsl-sai: new driver dt-bindings: clock: document the fsl-sai driver clk: composite: add _register_composite_pdata() variants * clk-qoriq: clk: qoriq: add ls1088a hwaccel clocks support clk: ls1028a: Add clock driver for Display output interface dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings --- db865ee447d46eccd641dc70c7f9acc231a3141e diff --cc include/linux/clk-provider.h index 3f66b5e440e7e,caf4b9df16ebe,caf4b9df16ebe,caf4b9df16ebe,caf4b9df16ebe,caf4b9df16ebe,e2e9d867df363,caf4b9df16ebe..952ac035bab9e --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@@@@@@@@ -1045,12 -746,50 -746,50 -746,50 -746,50 -746,50 -752,57 -746,50 +1051,19 @@@@@@@@@ struct clk *clk_register_composite_pdat void clk_unregister_composite(struct clk *clk); struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, const char * const *parent_names, int num_parents, + struct clk_hw *mux_hw, const struct clk_ops *mux_ops, + struct clk_hw *rate_hw, const struct clk_ops *rate_ops, + struct clk_hw *gate_hw, const struct clk_ops *gate_ops, + unsigned long flags); ----- -void clk_hw_unregister_composite(struct clk_hw *hw); ----- - ----- -/** ----- - * struct clk_gpio - gpio gated clock ----- - * ----- - * @hw: handle between common and hardware-specific interfaces ----- - * @gpiod: gpio descriptor ----- - * ----- - * Clock with a gpio control for enabling and disabling the parent clock ----- - * or switching between two parents by asserting or deasserting the gpio. ----- - * ----- - * Implements .enable, .disable and .is_enabled or ----- - * .get_parent, .set_parent and .determine_rate depending on which clk_ops ----- - * is used. ----- - */ ----- -struct clk_gpio { ----- - struct clk_hw hw; ----- - struct gpio_desc *gpiod; ----- -}; ----- - ----- -#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) ----- - ----- -extern const struct clk_ops clk_gpio_gate_ops; ----- -struct clk *clk_register_gpio_gate(struct device *dev, const char *name, ----- - const char *parent_name, struct gpio_desc *gpiod, ----- - unsigned long flags); ----- -struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, ----- - const char *parent_name, struct gpio_desc *gpiod, ----- - unsigned long flags); ----- -void clk_hw_unregister_gpio_gate(struct clk_hw *hw); ----- - ----- -extern const struct clk_ops clk_gpio_mux_ops; ----- -struct clk *clk_register_gpio_mux(struct device *dev, const char *name, ----- - const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, ----- - unsigned long flags); ----- -struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, ----- - const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, ++++++ +struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, ++++++ + const char *name, ++++++ + const struct clk_parent_data *parent_data, int num_parents, +++++ + struct clk_hw *mux_hw, const struct clk_ops *mux_ops, +++++ + struct clk_hw *rate_hw, const struct clk_ops *rate_ops, +++++ + struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); ----- -void clk_hw_unregister_gpio_mux(struct clk_hw *hw); +++++ +void clk_hw_unregister_composite(struct clk_hw *hw); - /** - * struct clk_gpio - gpio gated clock - * - * @hw: handle between common and hardware-specific interfaces - * @gpiod: gpio descriptor - * - * Clock with a gpio control for enabling and disabling the parent clock - * or switching between two parents by asserting or deasserting the gpio. - * - * Implements .enable, .disable and .is_enabled or - * .get_parent, .set_parent and .determine_rate depending on which clk_ops - * is used. - */ - struct clk_gpio { - struct clk_hw hw; - struct gpio_desc *gpiod; - }; - - #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) - - extern const struct clk_ops clk_gpio_gate_ops; - struct clk *clk_register_gpio_gate(struct device *dev, const char *name, - const char *parent_name, struct gpio_desc *gpiod, - unsigned long flags); - struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, - const char *parent_name, struct gpio_desc *gpiod, - unsigned long flags); - void clk_hw_unregister_gpio_gate(struct clk_hw *hw); - - extern const struct clk_ops clk_gpio_mux_ops; - struct clk *clk_register_gpio_mux(struct device *dev, const char *name, - const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, - unsigned long flags); - struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, - const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, - unsigned long flags); - void clk_hw_unregister_gpio_mux(struct clk_hw *hw); - struct clk *clk_register(struct device *dev, struct clk_hw *hw); struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);