From: Anthony Liguori <aliguori@us.ibm.com>
Date: Mon, 8 Jul 2013 13:00:23 +0000 (-0500)
Subject: Merge remote-tracking branch 'mst/tags/for_anthony' into staging
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=dc11549ec213f85f6a024c7df68d349464cd1688;p=qemu.git

Merge remote-tracking branch 'mst/tags/for_anthony' into staging

pci,misc enhancements

This includes some pci enhancements:

Better support for systems with multiple PCI root buses
FW cfg interface for more robust pci programming in BIOS
Minor fixes/cleanups for fw cfg and cross-version migration -
    because of dependencies with other patches

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Sun 07 Jul 2013 03:11:18 PM CDT using RSA key ID D28D5469
# gpg: Can't check signature: public key not found

# By David Gibson (10) and others
# Via Michael S. Tsirkin
* mst/tags/for_anthony:
  pci: Fold host_buses list into PCIHostState functionality
  pci: Remove domain from PCIHostBus
  pci: Simpler implementation of primary PCI bus
  pci: Add root bus parameter to pci_nic_init()
  pci: Add root bus argument to pci_get_bus_devfn()
  pci: Replace pci_find_domain() with more general pci_root_bus_path()
  pci: Use helper to find device's root bus in pci_find_domain()
  pci: Abolish pci_find_root_bus()
  pci: Move pci_read_devaddr to pci-hotplug-old.c
  pci: Cleanup configuration for pci-hotplug.c
  pvpanic: fix fwcfg for big endian hosts
  pvpanic: initialization cleanup
  MAINTAINERS: s/Marcelo/Paolo/
  e1000: cleanup process_tx_desc
  pc_piix: cleanup init compat handling
  pc: pass PCI hole ranges to Guests
  pci: store PCI hole ranges in guestinfo structure
  range: add Range structure

Message-id: 1373228271-31223-1-git-send-email-mst@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---

dc11549ec213f85f6a024c7df68d349464cd1688
diff --cc hw/pci-host/q35.c
index 5661ace80c,13148ed533..8c3ee535ff
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@@ -244,8 -253,16 +253,16 @@@ static int mch_init(PCIDevice *d
      hwaddr pci_hole64_size;
      MCHPCIState *mch = MCH_PCI_DEVICE(d);
  
+     /* Leave enough space for the biggest MCFG BAR */
+     /* TODO: this matches current bios behaviour, but
+      * it's not a power of two, which means an MTRR
+      * can't cover it exactly.
+      */
+     mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
+         MCH_HOST_BRIDGE_PCIEXBAR_MAX;
+ 
      /* setup pci memory regions */
 -    memory_region_init_alias(&mch->pci_hole, "pci-hole",
 +    memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole",
                               mch->pci_address_space,
                               mch->below_4g_mem_size,
                               0x100000000ULL - mch->below_4g_mem_size);