From: Alistair Francis <Alistair.Francis@wdc.com>
Date: Sat, 20 Apr 2019 02:27:43 +0000 (+0000)
Subject: target/riscv: Add the HGATP register masks
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=e06431108b0b1ef6ca76398d2b0b792ea24ae6bc;p=qemu.git

target/riscv: Add the HGATP register masks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a179137bc1..dc9d53d4be 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -208,6 +208,17 @@
 #define CSR_HIDELEG         0xa03
 #define CSR_HGATP           0xa80
 
+#if defined(TARGET_RISCV32)
+#define HGATP_MODE           SATP32_MODE
+#define HGATP_ASID           SATP32_ASID
+#define HGATP_PPN            SATP32_PPN
+#endif
+#if defined(TARGET_RISCV64)
+#define HGATP_MODE           SATP64_MODE
+#define HGATP_ASID           SATP64_ASID
+#define HGATP_PPN            SATP64_PPN
+#endif
+
 /* Performance Counters */
 #define CSR_MHPMCOUNTER3    0xb03
 #define CSR_MHPMCOUNTER4    0xb04