From: Sergio Paracuellos Date: Sat, 25 Sep 2021 20:32:24 +0000 (+0200) Subject: staging: mt7621-pci: properly adjust base address for the IO window X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=e0b913816ba1ab61fd57a0b14b354271cbe8f000;p=linux.git staging: mt7621-pci: properly adjust base address for the IO window The value to adjust in the bridge register RALINK_PCI_IOBASE must take into account the raw value from DT, not only the translated linux port number. As long as io_offset is zero, the two are the same, but if you were to use multiple host bridge in the system, or pick a different bus address in DT, you can have a nonzero io_offset. At this means to take into account the bus address which is used to calculate this offset, substracting it from the IO resource start address. Acked-by: Arnd Bergmann Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210925203224.10419-7-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 6acfc94a16e73..503cb1fca2e01 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -482,7 +482,7 @@ static int mt7621_pcie_enable_ports(struct pci_host_bridge *host) /* Setup MEMWIN and IOWIN */ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); - pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE); + pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE); list_for_each_entry(port, &pcie->ports, list) { if (port->enabled) {