From: Dan Williams <dan.j.williams@intel.com>
Date: Mon, 5 Dec 2022 20:31:30 +0000 (-0800)
Subject: Merge branch 'for-6.2/cxl-aer' into for-6.2/cxl
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=e0f6fa0d425f745a887e640be66e22b45451e169;p=linux.git

Merge branch 'for-6.2/cxl-aer' into for-6.2/cxl

Pick up CXL AER handling and correctable error extensions. Resolve
conflicts with cxl_pmem_wq reworks and RCH support.
---

e0f6fa0d425f745a887e640be66e22b45451e169
diff --cc drivers/cxl/cxlmem.h
index 710c7694bf9ff,b3117fd67f420..785c6c12515db
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@@ -199,9 -186,9 +199,10 @@@ struct cxl_endpoint_dvsec_info 
   * Currently only memory devices are represented.
   *
   * @dev: The device associated with this CXL state
+  * @cxlmd: The device representing the CXL.mem capabilities of @dev
   * @regs: Parsed register blocks
   * @cxl_dvsec: Offset to the PCIe device DVSEC
 + * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
   * @payload_size: Size of space for payload
   *                (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
   * @lsa_size: Size of Label Storage Area
diff --cc drivers/cxl/pci.c
index 73ff6c33a0c0f,36db681f3705f..6cec9fa9326c1
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@@ -433,15 -400,11 +405,20 @@@ static void devm_cxl_pci_create_doe(str
  	}
  }
  
 +/*
 + * Assume that any RCIEP that emits the CXL memory expander class code
 + * is an RCD
 + */
 +static bool is_cxl_restricted(struct pci_dev *pdev)
 +{
 +	return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END;
 +}
 +
+ static void disable_aer(void *pdev)
+ {
+ 	pci_disable_pcie_error_reporting(pdev);
+ }
+ 
  static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  {
  	struct cxl_register_map map;
@@@ -463,8 -426,8 +440,9 @@@
  	cxlds = cxl_dev_state_create(&pdev->dev);
  	if (IS_ERR(cxlds))
  		return PTR_ERR(cxlds);
+ 	pci_set_drvdata(pdev, cxlds);
  
 +	cxlds->rcd = is_cxl_restricted(pdev);
  	cxlds->serial = pci_get_dsn(pdev);
  	cxlds->cxl_dvsec = pci_find_dvsec_capability(
  		pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
@@@ -513,6 -481,17 +496,14 @@@
  	if (IS_ERR(cxlmd))
  		return PTR_ERR(cxlmd);
  
+ 	if (cxlds->regs.ras) {
+ 		pci_enable_pcie_error_reporting(pdev);
+ 		rc = devm_add_action_or_reset(&pdev->dev, disable_aer, pdev);
+ 		if (rc)
+ 			return rc;
+ 	}
+ 	pci_save_state(pdev);
+ 
 -	if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM))
 -		rc = devm_cxl_add_nvdimm(&pdev->dev, cxlmd);
 -
  	return rc;
  }