From: Oliver Upton <oliver.upton@linux.dev>
Date: Thu, 15 Jun 2023 13:09:21 +0000 (+0000)
Subject: Merge branch kvm-arm64/misc into kvmarm/next
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=e1e315c4d5282c1713ab08acec2ac17b8dbd6591;p=linux.git

Merge branch kvm-arm64/misc into kvmarm/next

* kvm-arm64/misc:
  : Miscellaneous updates
  :
  :  - Avoid trapping CTR_EL0 on systems with FEAT_EVT, as the register is
  :    commonly read by userspace
  :
  :  - Make use of FEAT_BTI at hyp stage-1, setting the Guard Page bit to 1
  :    for executable mappings
  :
  :  - Use a separate set of pointer authentication keys for the hypervisor
  :    when running in protected mode (i.e. pKVM)
  :
  :  - Plug a few holes in timer initialization where KVM fails to free the
  :    timer IRQ(s)
  KVM: arm64: Use different pointer authentication keys for pKVM
  KVM: arm64: timers: Fix resource leaks in kvm_timer_hyp_init()
  KVM: arm64: Use BTI for nvhe
  KVM: arm64: Relax trapping of CTR_EL0 when FEAT_EVT is available

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---

e1e315c4d5282c1713ab08acec2ac17b8dbd6591
diff --cc arch/arm64/kernel/cpufeature.c
index c01c52a3dd7e3,4a2ab3f366de1..3d93147179a00
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@@ -2656,12 -2641,17 +2656,23 @@@ static const struct arm64_cpu_capabilit
  		.cpu_enable = cpu_enable_dit,
  		ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
  	},
 +	{
 +		.desc = "VHE for hypervisor only",
 +		.capability = ARM64_KVM_HVHE,
 +		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
 +		.matches = hvhe_possible,
 +	},
+ 	{
+ 		.desc = "Enhanced Virtualization Traps",
+ 		.capability = ARM64_HAS_EVT,
+ 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ 		.sys_reg = SYS_ID_AA64MMFR2_EL1,
+ 		.sign = FTR_UNSIGNED,
+ 		.field_pos = ID_AA64MMFR2_EL1_EVT_SHIFT,
+ 		.field_width = 4,
+ 		.min_field_value = ID_AA64MMFR2_EL1_EVT_IMP,
+ 		.matches = has_cpuid_feature,
+ 	},
  	{},
  };