From: Alim Akhtar Date: Fri, 10 Jun 2022 10:41:15 +0000 (+0530) Subject: phy: samsung-ufs: move cdr offset to drvdata X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=e313216b52813a9c51cad0bf406b60d3248b268f;p=linux.git phy: samsung-ufs: move cdr offset to drvdata Move CDR lock offset to drv data so that it can be extended for other SoCs which are having CDR lock at different register offset. Signed-off-by: Bharat Uppal Signed-off-by: Alim Akhtar Reviewed-by: Chanho Park Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220610104119.66401-3-alim.akhtar@samsung.com Signed-off-by: Vinod Koul --- diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c index d1e9d0ae5c1dd..72854336f59d8 100644 --- a/drivers/phy/samsung/phy-exynos7-ufs.c +++ b/drivers/phy/samsung/phy-exynos7-ufs.c @@ -11,6 +11,8 @@ #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e + /* Calibration for phy initialization */ static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = { PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), @@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = { .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN, }, .has_symbol_clk = 1, + .cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, }; diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c index fa4d2983eec68..2b256070d657f 100644 --- a/drivers/phy/samsung/phy-exynosautov9-ufs.c +++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c @@ -10,6 +10,7 @@ #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \ PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) @@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = { .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN, }, .has_symbol_clk = 0, + .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, }; diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c index 206a79c69a6ce..8cec7652b459d 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.c +++ b/drivers/phy/samsung/phy-samsung-ufs.c @@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy) } err = readl_poll_timeout( - ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS), + ufs_phy->reg_pma + + PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset), val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us); if (err) dev_err(ufs_phy->dev, @@ -327,6 +328,7 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev) drvdata = match->data; phy->dev = dev; + phy->drvdata = drvdata; phy->cfgs = drvdata->cfgs; phy->has_symbol_clk = drvdata->has_symbol_clk; memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol)); diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h index 854b53bdf3478..913542ebff7a9 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.h +++ b/drivers/phy/samsung/phy-samsung-ufs.h @@ -40,7 +40,6 @@ /* UFS PHY registers */ #define PHY_PLL_LOCK_STATUS 0x1e -#define PHY_CDR_LOCK_STATUS 0x5e #define PHY_PLL_LOCK_BIT BIT(5) #define PHY_CDR_LOCK_BIT BIT(4) @@ -111,6 +110,7 @@ struct samsung_ufs_phy_drvdata { const struct samsung_ufs_phy_cfg **cfgs; struct samsung_ufs_phy_pmu_isol isol; bool has_symbol_clk; + u32 cdr_lock_status_offset; }; struct samsung_ufs_phy {