From: Marc Zyngier Date: Thu, 12 Aug 2021 19:02:13 +0000 (+0100) Subject: arm64: Document the requirement for SCR_EL3.HCE X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=e3849765037b85e61b2432ded488ee9fb3ff126d;p=linux.git arm64: Document the requirement for SCR_EL3.HCE It is amazing that we never documented this absolutely basic requirement: if you boot the kernel at EL2, you'd better enable the HVC instruction from EL3. Really, just do it. Signed-off-by: Marc Zyngier Acked-by: Mark Rutland Link: https://lore.kernel.org/r/20210812190213.2601506-6-maz@kernel.org Signed-off-by: Catalin Marinas --- diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 5822d6da9fa6f..3f9d86557c5e0 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -207,10 +207,17 @@ Before jumping into the kernel, the following conditions must be met: software at a higher exception level to prevent execution in an UNKNOWN state. - - SCR_EL3.FIQ must have the same value across all CPUs the kernel is - executing on. - - The value of SCR_EL3.FIQ must be the same as the one present at boot - time whenever the kernel is executing. + For all systems: + - If EL3 is present: + + - SCR_EL3.FIQ must have the same value across all CPUs the kernel is + executing on. + - The value of SCR_EL3.FIQ must be the same as the one present at boot + time whenever the kernel is executing. + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.HCE (bit 8) must be initialised to 0b1. For systems with a GICv3 interrupt controller to be used in v3 mode: - If EL3 is present: