From: Doug Brown Date: Mon, 16 Jan 2023 19:43:58 +0000 (-0800) Subject: mmc: sdhci-pxav2: add optional core clock X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=e41c48b4bcb3ceee43a101ba7d514483271fb2fb;p=linux.git mmc: sdhci-pxav2: add optional core clock Add ability to have an optional core clock just like the pxav3 driver. The PXA168 needs this because its SDHC controllers have separate core and io clocks that both need to be enabled. This also correctly matches the documented devicetree bindings for this driver. Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Doug Brown Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/20230116194401.20372-6-doug@schmorgal.com Signed-off-by: Ulf Hansson --- diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index f5c86e1ba7341..3141901e1558b 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -191,7 +191,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) const struct sdhci_pxa_variant *variant; int ret; - struct clk *clk; + struct clk *clk, *clk_core; host = sdhci_pltfm_init(pdev, NULL, 0); if (IS_ERR(host)) @@ -214,6 +214,13 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) goto free; } + clk_core = devm_clk_get_optional_enabled(dev, "core"); + if (IS_ERR(clk_core)) { + ret = PTR_ERR(clk_core); + dev_err_probe(dev, ret, "failed to enable core clock\n"); + goto disable_clk; + } + host->quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;