From: Jonathan Cameron Date: Sun, 7 Aug 2022 15:12:16 +0000 (+0100) Subject: staging: iio: frequency: ad9834: Fix alignment for DMA safety X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=e48668a38bf420c660b07851985e6922fcf4b194;p=linux.git staging: iio: frequency: ad9834: Fix alignment for DMA safety ____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Signed-off-by: Jonathan Cameron Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20220807151218.656881-3-jic23@kernel.org --- diff --git a/drivers/staging/iio/frequency/ad9834.c b/drivers/staging/iio/frequency/ad9834.c index 94b131ef8a22c..2b4267a87e65e 100644 --- a/drivers/staging/iio/frequency/ad9834.c +++ b/drivers/staging/iio/frequency/ad9834.c @@ -83,7 +83,7 @@ struct ad9834_state { * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. */ - __be16 data ____cacheline_aligned; + __be16 data __aligned(IIO_DMA_MINALIGN); __be16 freq_data[2]; };