From: Ville Syrjälä Date: Wed, 22 Jun 2022 15:54:50 +0000 (+0300) Subject: drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platforms X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=eadbd867177e1d72b2ff71b7ba0dffcae4dabc64;p=linux.git drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platforms Like most other plane control register bits, the pipe gamma enable bit is also blocked by CxSR. So make sure we kick the machine out of CxSR before trying to change that bit. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20220622155452.32587-8-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy --- diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index fc23d5d8f7fd8..123c57ceeb736 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1287,6 +1287,10 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) return PTR_ERR(plane_state); new_crtc_state->update_planes |= BIT(plane->id); + + /* plane control register changes blocked by CxSR */ + if (HAS_GMCH(dev_priv)) + new_crtc_state->disable_cxsr = true; } return 0;