From: Sergio Paracuellos Date: Sat, 25 Sep 2021 20:32:21 +0000 (+0200) Subject: MIPS: ralink: set PCI_IOBASE to 'mips_io_port_base' X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=ebe7e788ee7270cfe43584e99f11b00d1e4bbb3f;p=linux.git MIPS: ralink: set PCI_IOBASE to 'mips_io_port_base' By default MIPS architecture use function 'set_io_port_base()' to set the virtual address of the first IO port. This function at the end sets variable 'mips_io_port_base' with the desired address. To align things and allow to change first IO port location address for PCI, set PCI_IOBASE definition as 'mips_io_port_base'. Fixes: 222b27713d7f ("MIPS: ralink: Define PCI_IOBASE") Acked-by: Arnd Bergmann Acked-by: Thomas Bogendoerfer Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210925203224.10419-4-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman --- diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h index 87d085c9ad610..05d14c21c4178 100644 --- a/arch/mips/include/asm/mach-ralink/spaces.h +++ b/arch/mips/include/asm/mach-ralink/spaces.h @@ -2,8 +2,8 @@ #ifndef __ASM_MACH_RALINK_SPACES_H_ #define __ASM_MACH_RALINK_SPACES_H_ -#define PCI_IOBASE _AC(0xa0000000, UL) -#define PCI_IOSIZE SZ_16M +#define PCI_IOBASE mips_io_port_base +#define PCI_IOSIZE SZ_64K #define IO_SPACE_LIMIT (PCI_IOSIZE - 1) #include