From: Costa Shulyupin Date: Tue, 25 Jul 2023 04:38:03 +0000 (+0300) Subject: docs: move mips under arch X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=ec62a746b65363f6078fb1eefc7faffe1a4cdc38;p=linux.git docs: move mips under arch and fix all in-tree references. Architecture-specific documentation is being moved into Documentation/arch/ as a way of cleaning up the top-level documentation directory and making the docs hierarchy more closely match the source hierarchy. Signed-off-by: Costa Shulyupin Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20230725043835.2249678-1-costa.shul@redhat.com --- diff --git a/Documentation/arch/index.rst b/Documentation/arch/index.rst index 4b6b1beebad6d..dc59634c5fbb4 100644 --- a/Documentation/arch/index.rst +++ b/Documentation/arch/index.rst @@ -15,7 +15,7 @@ implementation. ia64/index loongarch/index m68k/index - ../mips/index + mips/index nios2/index openrisc/index parisc/index diff --git a/Documentation/arch/mips/booting.rst b/Documentation/arch/mips/booting.rst new file mode 100644 index 0000000000000..7c18a4eab48b6 --- /dev/null +++ b/Documentation/arch/mips/booting.rst @@ -0,0 +1,28 @@ +.. SPDX-License-Identifier: GPL-2.0 + +BMIPS DeviceTree Booting +------------------------ + + Some bootloaders only support a single entry point, at the start of the + kernel image. Other bootloaders will jump to the ELF start address. + Both schemes are supported; CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, + so the first instruction immediately jumps to kernel_entry(). + + Similar to the arch/arm case (b), a DT-aware bootloader is expected to + set up the following registers: + + a0 : 0 + + a1 : 0xffffffff + + a2 : Physical pointer to the device tree block (defined in chapter + II) in RAM. The device tree can be located anywhere in the first + 512MB of the physical address space (0x00000000 - 0x1fffffff), + aligned on a 64 bit boundary. + + Legacy bootloaders do not use this convention, and they do not pass in a + DT block. In this case, Linux will look for a builtin DTB, selected via + CONFIG_DT_*. + + This convention is defined for 32-bit systems only, as there are not + currently any 64-bit BMIPS implementations. diff --git a/Documentation/arch/mips/features.rst b/Documentation/arch/mips/features.rst new file mode 100644 index 0000000000000..1973d729b29a9 --- /dev/null +++ b/Documentation/arch/mips/features.rst @@ -0,0 +1,3 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. kernel-feat:: $srctree/Documentation/features mips diff --git a/Documentation/arch/mips/index.rst b/Documentation/arch/mips/index.rst new file mode 100644 index 0000000000000..037f85a08fe3b --- /dev/null +++ b/Documentation/arch/mips/index.rst @@ -0,0 +1,21 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=========================== +MIPS-specific Documentation +=========================== + +.. toctree:: + :maxdepth: 2 + :numbered: + + booting + ingenic-tcu + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/arch/mips/ingenic-tcu.rst b/Documentation/arch/mips/ingenic-tcu.rst new file mode 100644 index 0000000000000..2ce4cb1314dc4 --- /dev/null +++ b/Documentation/arch/mips/ingenic-tcu.rst @@ -0,0 +1,71 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============================================== +Ingenic JZ47xx SoCs Timer/Counter Unit hardware +=============================================== + +The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function +hardware block. It features up to eight channels, that can be used as +counters, timers, or PWM. + +- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all + have eight channels. + +- JZ4725B introduced a separate channel, called Operating System Timer + (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is + 64-bit. + +- Each one of the TCU channels has its own clock, which can be reparented to three + different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register. + + - The watchdog and OST hardware blocks also feature a TCSR register with the same + format in their register space. + - The TCU registers used to gate/ungate can also gate/ungate the watchdog and + OST clocks. + +- Each TCU channel works in one of two modes: + + - mode TCU1: channels cannot work in sleep mode, but are easier to + operate. + - mode TCU2: channels can work in sleep mode, but the operation is a bit + more complicated than with TCU1 channels. + +- The mode of each TCU channel depends on the SoC used: + + - On the oldest SoCs (up to JZ4740), all of the eight channels operate in + TCU1 mode. + - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. + - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the + others operate as TCU1. + +- Each channel can generate an interrupt. Some channels share an interrupt + line, some don't, and this changes between SoC versions: + + - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their + own interrupt line; channels 2-7 share the last interrupt line. + - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one + interrupt line; the OST uses the last interrupt line. + - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; + channels 0-4 and (if eight channels) 6-7 all share one interrupt line; + the OST uses the last interrupt line. + +Implementation +============== + +The functionalities of the TCU hardware are spread across multiple drivers: + +=========== ===== +clocks drivers/clk/ingenic/tcu.c +interrupts drivers/irqchip/irq-ingenic-tcu.c +timers drivers/clocksource/ingenic-timer.c +OST drivers/clocksource/ingenic-ost.c +PWM drivers/pwm/pwm-jz4740.c +watchdog drivers/watchdog/jz4740_wdt.c +=========== ===== + +Because various functionalities of the TCU that belong to different drivers +and frameworks can be controlled from the same registers, all of these +drivers access their registers through the same regmap. + +For more information regarding the devicetree bindings of the TCU drivers, +have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml. diff --git a/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml b/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml index 2d14610888a71..585b5f5217c48 100644 --- a/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml +++ b/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml @@ -8,7 +8,7 @@ title: Ingenic SoCs Timer/Counter Unit (TCU) description: | For a description of the TCU hardware and drivers, have a look at - Documentation/mips/ingenic-tcu.rst. + Documentation/arch/mips/ingenic-tcu.rst. maintainers: - Paul Cercueil diff --git a/Documentation/mips/booting.rst b/Documentation/mips/booting.rst deleted file mode 100644 index 7c18a4eab48b6..0000000000000 --- a/Documentation/mips/booting.rst +++ /dev/null @@ -1,28 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -BMIPS DeviceTree Booting ------------------------- - - Some bootloaders only support a single entry point, at the start of the - kernel image. Other bootloaders will jump to the ELF start address. - Both schemes are supported; CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, - so the first instruction immediately jumps to kernel_entry(). - - Similar to the arch/arm case (b), a DT-aware bootloader is expected to - set up the following registers: - - a0 : 0 - - a1 : 0xffffffff - - a2 : Physical pointer to the device tree block (defined in chapter - II) in RAM. The device tree can be located anywhere in the first - 512MB of the physical address space (0x00000000 - 0x1fffffff), - aligned on a 64 bit boundary. - - Legacy bootloaders do not use this convention, and they do not pass in a - DT block. In this case, Linux will look for a builtin DTB, selected via - CONFIG_DT_*. - - This convention is defined for 32-bit systems only, as there are not - currently any 64-bit BMIPS implementations. diff --git a/Documentation/mips/features.rst b/Documentation/mips/features.rst deleted file mode 100644 index 1973d729b29a9..0000000000000 --- a/Documentation/mips/features.rst +++ /dev/null @@ -1,3 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. kernel-feat:: $srctree/Documentation/features mips diff --git a/Documentation/mips/index.rst b/Documentation/mips/index.rst deleted file mode 100644 index 037f85a08fe3b..0000000000000 --- a/Documentation/mips/index.rst +++ /dev/null @@ -1,21 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -=========================== -MIPS-specific Documentation -=========================== - -.. toctree:: - :maxdepth: 2 - :numbered: - - booting - ingenic-tcu - - features - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/mips/ingenic-tcu.rst b/Documentation/mips/ingenic-tcu.rst deleted file mode 100644 index 2ce4cb1314dc4..0000000000000 --- a/Documentation/mips/ingenic-tcu.rst +++ /dev/null @@ -1,71 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -=============================================== -Ingenic JZ47xx SoCs Timer/Counter Unit hardware -=============================================== - -The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function -hardware block. It features up to eight channels, that can be used as -counters, timers, or PWM. - -- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all - have eight channels. - -- JZ4725B introduced a separate channel, called Operating System Timer - (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is - 64-bit. - -- Each one of the TCU channels has its own clock, which can be reparented to three - different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register. - - - The watchdog and OST hardware blocks also feature a TCSR register with the same - format in their register space. - - The TCU registers used to gate/ungate can also gate/ungate the watchdog and - OST clocks. - -- Each TCU channel works in one of two modes: - - - mode TCU1: channels cannot work in sleep mode, but are easier to - operate. - - mode TCU2: channels can work in sleep mode, but the operation is a bit - more complicated than with TCU1 channels. - -- The mode of each TCU channel depends on the SoC used: - - - On the oldest SoCs (up to JZ4740), all of the eight channels operate in - TCU1 mode. - - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. - - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the - others operate as TCU1. - -- Each channel can generate an interrupt. Some channels share an interrupt - line, some don't, and this changes between SoC versions: - - - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their - own interrupt line; channels 2-7 share the last interrupt line. - - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one - interrupt line; the OST uses the last interrupt line. - - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; - channels 0-4 and (if eight channels) 6-7 all share one interrupt line; - the OST uses the last interrupt line. - -Implementation -============== - -The functionalities of the TCU hardware are spread across multiple drivers: - -=========== ===== -clocks drivers/clk/ingenic/tcu.c -interrupts drivers/irqchip/irq-ingenic-tcu.c -timers drivers/clocksource/ingenic-timer.c -OST drivers/clocksource/ingenic-ost.c -PWM drivers/pwm/pwm-jz4740.c -watchdog drivers/watchdog/jz4740_wdt.c -=========== ===== - -Because various functionalities of the TCU that belong to different drivers -and frameworks can be controlled from the same registers, all of these -drivers access their registers through the same regmap. - -For more information regarding the devicetree bindings of the TCU drivers, -have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml. diff --git a/Documentation/translations/zh_CN/arch/index.rst b/Documentation/translations/zh_CN/arch/index.rst index d4c1c729dde20..e3d273d7d599e 100644 --- a/Documentation/translations/zh_CN/arch/index.rst +++ b/Documentation/translations/zh_CN/arch/index.rst @@ -8,7 +8,7 @@ .. toctree:: :maxdepth: 2 - ../mips/index + mips/index arm64/index ../riscv/index openrisc/index diff --git a/Documentation/translations/zh_CN/arch/mips/booting.rst b/Documentation/translations/zh_CN/arch/mips/booting.rst new file mode 100644 index 0000000000000..485b57e0ca0b2 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/mips/booting.rst @@ -0,0 +1,34 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/mips/booting.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_booting: + +BMIPS设备树引导 +------------------------ + + 一些bootloaders只支持在内核镜像开始地址处的单一入口点。而其它 + bootloaders将跳转到ELF的开始地址处。两种方案都支持的；因为 + CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, 所以第一条指令 + 会立即跳转到kernel_entry()入口处执行。 + + 与arch/arm情况(b)类似，dt感知的引导加载程序需要设置以下寄存器: + + a0 : 0 + + a1 : 0xffffffff + + a2 : RAM中指向设备树块的物理指针(在chapterII中定义)。 + 设备树可以位于前512MB物理地址空间(0x00000000 - + 0x1fffffff)的任何位置，以64位边界对齐。 + + 传统bootloaders不会使用这样的约定，并且它们不传入DT块。 + 在这种情况下，Linux将通过选中CONFIG_DT_*查找DTB。 + + 以上约定只在32位系统中定义，因为目前没有任何64位的BMIPS实现。 diff --git a/Documentation/translations/zh_CN/arch/mips/features.rst b/Documentation/translations/zh_CN/arch/mips/features.rst new file mode 100644 index 0000000000000..da1b956e4a40f --- /dev/null +++ b/Documentation/translations/zh_CN/arch/mips/features.rst @@ -0,0 +1,13 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/mips/features.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_features: + +.. kernel-feat:: $srctree/Documentation/features mips diff --git a/Documentation/translations/zh_CN/arch/mips/index.rst b/Documentation/translations/zh_CN/arch/mips/index.rst new file mode 100644 index 0000000000000..2a34217119eaf --- /dev/null +++ b/Documentation/translations/zh_CN/arch/mips/index.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/mips/index.rst + +:翻译: + + 司延腾 Yanteng Si + +=========================== +MIPS特性文档 +=========================== + +.. toctree:: + :maxdepth: 2 + :numbered: + + booting + ingenic-tcu + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/arch/mips/ingenic-tcu.rst b/Documentation/translations/zh_CN/arch/mips/ingenic-tcu.rst new file mode 100644 index 0000000000000..3d599a36b5717 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/mips/ingenic-tcu.rst @@ -0,0 +1,72 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/mips/ingenic-tcu.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_ingenic-tcu: + +=============================================== +君正 JZ47xx SoC定时器/计数器硬件单元 +=============================================== + +君正 JZ47xx SoC中的定时器/计数器单元(TCU)是一个多功能硬件块。它有多达 +8个通道，可以用作计数器，计时器，或脉冲宽度调制器。 + +- JZ4725B, JZ4750, JZ4755 只有６个TCU通道。其它SoC都有８个通道。 + +- JZ4725B引入了一个独立的通道，称为操作系统计时器(OST)。这是一个32位可 + 编程定时器。在JZ4760B及以上型号上，它是64位的。 + +- 每个TCU通道都有自己的时钟源，可以通过 TCSR 寄存器设置通道的父级时钟 + 源（pclk、ext、rtc）、开关以及分频。 + + - 看门狗和OST硬件模块在它们的寄存器空间中也有相同形式的TCSR寄存器。 + - 用于关闭/开启的 TCU 寄存器也可以关闭/开启看门狗和 OST 时钟。 + +- 每个TCU通道在两种模式的其中一种模式下运行： + + - 模式 TCU1：通道无法在睡眠模式下运行，但更易于操作。 + - 模式 TCU2：通道可以在睡眠模式下运行，但操作比 TCU1 通道复杂一些。 + +- 每个 TCU 通道的模式取决于使用的SoC： + + - 在最老的SoC（高于JZ4740），八个通道都运行在TCU1模式。 + - 在 JZ4725B，通道5运行在TCU2,其它通道则运行在TCU1。 + - 在最新的SoC（JZ4750及之后），通道1-2运行在TCU2，其它通道则运行 + 在TCU1。 + +- 每个通道都可以生成中断。有些通道共享一条中断线，而有些没有，其在SoC型 + 号之间的变更： + + - 在很老的SoC（JZ4740及更低），通道0和通道1有它们自己的中断线；通 + 道2-7共享最后一条中断线。 + - 在 JZ4725B，通道0有它自己的中断线；通道1-5共享一条中断线；OST + 使用最后一条中断线。 + - 在比较新的SoC（JZ4750及以后），通道5有它自己的中断线；通 + 道0-4和（如果是8通道）6-7全部共享一条中断线；OST使用最后一条中 + 断线。 + +实现 +==== + +TCU硬件的功能分布在多个驱动程序： + +============== =================================== +时钟 drivers/clk/ingenic/tcu.c +中断 drivers/irqchip/irq-ingenic-tcu.c +定时器 drivers/clocksource/ingenic-timer.c +OST drivers/clocksource/ingenic-ost.c +脉冲宽度调制器 drivers/pwm/pwm-jz4740.c +看门狗 drivers/watchdog/jz4740_wdt.c +============== =================================== + +因为可以从相同的寄存器控制属于不同驱动程序和框架的TCU的各种功能，所以 +所有这些驱动程序都通过相同的控制总线通用接口访问它们的寄存器。 + +有关TCU驱动程序的设备树绑定的更多信息，请参阅: +Documentation/devicetree/bindings/timer/ingenic,tcu.yaml. diff --git a/Documentation/translations/zh_CN/mips/booting.rst b/Documentation/translations/zh_CN/mips/booting.rst deleted file mode 100644 index e0bbd3f208625..0000000000000 --- a/Documentation/translations/zh_CN/mips/booting.rst +++ /dev/null @@ -1,34 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/mips/booting.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_booting: - -BMIPS设备树引导 ------------------------- - - 一些bootloaders只支持在内核镜像开始地址处的单一入口点。而其它 - bootloaders将跳转到ELF的开始地址处。两种方案都支持的；因为 - CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, 所以第一条指令 - 会立即跳转到kernel_entry()入口处执行。 - - 与arch/arm情况(b)类似，dt感知的引导加载程序需要设置以下寄存器: - - a0 : 0 - - a1 : 0xffffffff - - a2 : RAM中指向设备树块的物理指针(在chapterII中定义)。 - 设备树可以位于前512MB物理地址空间(0x00000000 - - 0x1fffffff)的任何位置，以64位边界对齐。 - - 传统bootloaders不会使用这样的约定，并且它们不传入DT块。 - 在这种情况下，Linux将通过选中CONFIG_DT_*查找DTB。 - - 以上约定只在32位系统中定义，因为目前没有任何64位的BMIPS实现。 diff --git a/Documentation/translations/zh_CN/mips/features.rst b/Documentation/translations/zh_CN/mips/features.rst deleted file mode 100644 index b61dab06ceaf4..0000000000000 --- a/Documentation/translations/zh_CN/mips/features.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/mips/features.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_features: - -.. kernel-feat:: $srctree/Documentation/features mips diff --git a/Documentation/translations/zh_CN/mips/index.rst b/Documentation/translations/zh_CN/mips/index.rst deleted file mode 100644 index 192c6adbb72e1..0000000000000 --- a/Documentation/translations/zh_CN/mips/index.rst +++ /dev/null @@ -1,29 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/mips/index.rst - -:翻译: - - 司延腾 Yanteng Si - -=========================== -MIPS特性文档 -=========================== - -.. toctree:: - :maxdepth: 2 - :numbered: - - booting - ingenic-tcu - - features - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/mips/ingenic-tcu.rst b/Documentation/translations/zh_CN/mips/ingenic-tcu.rst deleted file mode 100644 index ddbe149c517b2..0000000000000 --- a/Documentation/translations/zh_CN/mips/ingenic-tcu.rst +++ /dev/null @@ -1,72 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/mips/ingenic-tcu.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_ingenic-tcu: - -=============================================== -君正 JZ47xx SoC定时器/计数器硬件单元 -=============================================== - -君正 JZ47xx SoC中的定时器/计数器单元(TCU)是一个多功能硬件块。它有多达 -8个通道，可以用作计数器，计时器，或脉冲宽度调制器。 - -- JZ4725B, JZ4750, JZ4755 只有６个TCU通道。其它SoC都有８个通道。 - -- JZ4725B引入了一个独立的通道，称为操作系统计时器(OST)。这是一个32位可 - 编程定时器。在JZ4760B及以上型号上，它是64位的。 - -- 每个TCU通道都有自己的时钟源，可以通过 TCSR 寄存器设置通道的父级时钟 - 源（pclk、ext、rtc）、开关以及分频。 - - - 看门狗和OST硬件模块在它们的寄存器空间中也有相同形式的TCSR寄存器。 - - 用于关闭/开启的 TCU 寄存器也可以关闭/开启看门狗和 OST 时钟。 - -- 每个TCU通道在两种模式的其中一种模式下运行： - - - 模式 TCU1：通道无法在睡眠模式下运行，但更易于操作。 - - 模式 TCU2：通道可以在睡眠模式下运行，但操作比 TCU1 通道复杂一些。 - -- 每个 TCU 通道的模式取决于使用的SoC： - - - 在最老的SoC（高于JZ4740），八个通道都运行在TCU1模式。 - - 在 JZ4725B，通道5运行在TCU2,其它通道则运行在TCU1。 - - 在最新的SoC（JZ4750及之后），通道1-2运行在TCU2，其它通道则运行 - 在TCU1。 - -- 每个通道都可以生成中断。有些通道共享一条中断线，而有些没有，其在SoC型 - 号之间的变更： - - - 在很老的SoC（JZ4740及更低），通道0和通道1有它们自己的中断线；通 - 道2-7共享最后一条中断线。 - - 在 JZ4725B，通道0有它自己的中断线；通道1-5共享一条中断线；OST - 使用最后一条中断线。 - - 在比较新的SoC（JZ4750及以后），通道5有它自己的中断线；通 - 道0-4和（如果是8通道）6-7全部共享一条中断线；OST使用最后一条中 - 断线。 - -实现 -==== - -TCU硬件的功能分布在多个驱动程序： - -============== =================================== -时钟 drivers/clk/ingenic/tcu.c -中断 drivers/irqchip/irq-ingenic-tcu.c -定时器 drivers/clocksource/ingenic-timer.c -OST drivers/clocksource/ingenic-ost.c -脉冲宽度调制器 drivers/pwm/pwm-jz4740.c -看门狗 drivers/watchdog/jz4740_wdt.c -============== =================================== - -因为可以从相同的寄存器控制属于不同驱动程序和框架的TCU的各种功能，所以 -所有这些驱动程序都通过相同的控制总线通用接口访问它们的寄存器。 - -有关TCU驱动程序的设备树绑定的更多信息，请参阅: -Documentation/devicetree/bindings/timer/ingenic,tcu.yaml. diff --git a/MAINTAINERS b/MAINTAINERS index e481db8bd9376..dccce01f3dc96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14161,7 +14161,7 @@ W: http://www.linux-mips.org/ Q: https://patchwork.kernel.org/project/linux-mips/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git F: Documentation/devicetree/bindings/mips/ -F: Documentation/mips/ +F: Documentation/arch/mips/ F: arch/mips/ F: drivers/platform/mips/ F: include/dt-bindings/mips/