From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: Wed, 2 Dec 2020 17:53:20 +0000 (+0100)
Subject: target/mips: Do not initialize MT registers if MT ASE absent
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=ecc268e7c2488c0285684fad6d04cac6a794991d;p=qemu.git

target/mips: Do not initialize MT registers if MT ASE absent

Do not initialize MT-related config registers if the MT ASE
is not present. As some functions access the 'mvp' structure,
we still zero-allocate it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-4-f4bug@amsat.org>
---

diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 5a926bc6df..f72fee3b40 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -993,6 +993,10 @@ static void mvp_init(CPUMIPSState *env)
 {
     env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
 
+    if (!ase_mt_available(env)) {
+        return;
+    }
+
     /* MVPConf1 implemented, TLB sharable, no gating storage support,
        programmable cache partitioning implemented, number of allocatable
        and shareable TLB entries, MVP has allocatable TCs, 2 VPEs