From: Enric Balletbo i Serra Date: Thu, 9 Jul 2020 09:05:29 +0000 (+0200) Subject: dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=ed279529754d0c94115de5317e369d25468547c9;p=linux.git dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU general register files to know the DRAM type, so add a phandle to the syscon that manages these registers. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Chanwoo Choi Acked-by: Rob Herring Signed-off-by: Gaël PORTAY Acked-by: MyungJoo Ham Signed-off-by: Chanwoo Choi --- diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt index 0ec68141f85a7..a10d1f6d85c64 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -18,6 +18,8 @@ Optional properties: format depends on the interrupt controller. It should be a DCF interrupt. When DDR DVFS finishes a DCF interrupt is triggered. +- rockchip,pmu: Phandle to the syscon managing the "PMU general register + files". Following properties relate to DDR timing: