From: Stafford Horne <shorne@gmail.com>
Date: Fri, 14 Apr 2017 22:25:32 +0000 (+0900)
Subject: target/openrisc: add numcores and coreid support
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=ef3f5b9e7f83262e1eaea884b0a562b9fa73859c;p=qemu.git

target/openrisc: add numcores and coreid support

These are used to identify the processor in SMP system.  Their
definition has been defined in verilog cores but it not yet part of the
spec but it will be soon.

The proposal for this is available:
  https://openrisc.io/proposals/core-identifier-and-number-of-cores

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 6ba816249b..e13666bea0 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -233,6 +233,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 64): /* ESR */
         return env->esr;
 
+    case TO_SPR(0, 128): /* COREID */
+        return 0;
+
+    case TO_SPR(0, 129): /* NUMCORES */
+        return 1;
+
     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
         idx = spr - TO_SPR(1, 512);
         return env->tlb->dtlb[0][idx].mr;