From: Phil Edworthy Date: Wed, 18 May 2022 15:01:05 +0000 (+0100) Subject: clk: renesas: r9a09g011: Add WDT clock and reset entries X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=efded37b426f4e1b7b004b1e9924ff4bf16ec0fd;p=linux.git clk: renesas: r9a09g011: Add WDT clock and reset entries Add WDT0 clock and reset entries to CPG driver. Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220518150105.48167-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index b01d79a73dd86..b21915cf66487 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -132,6 +132,8 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), + DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), + DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), @@ -141,6 +143,7 @@ static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), + DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19), }; static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {